This group of commands manipulates IDT entries 0 through e to point to Kernel Debugger supplied interrupt handlers. By this means the Kernel Debugger may selectively be made to intercept each system exception before the system is allowed to process the exception. When a system exception is intercepted the Kernel Debugger gives control to the user. The original IDT entries are retained so that they may be re-instated, or given control following an exception which the Kernel Debugger has been intercepted. See the GT and TT commands for information in returning control to the system exception handlers.
Syntax:
────── V ─┬── L ──┬──┬───────┬───┬────────────────────┬───── ├── S ──┤ ├── R ──┤ ├──── interrupt ──┬──┤ ├── T ──┤ ├── V ──┤ │ │ │ └── C ──┘ ├── P ──┤ │ └───── , ──────┘ │ ├── F ──┤ └──────── * ─────────┘ ├── N ──┤ └── U ──┘
Parameters:
L
Only a category specification (R, V, P, F or N) may be optionally specified with the List subcommand.
If no refining category is specified then the vector subcommand being executed applies to the R, V, P and F options simultaneously.
Note: This option was introduced with OS/2 Warp V3.0 fix pack 26 and OS/2 Warp V4.0 fix pack 1.
The N option works in conjunction with the four refining categories, that is, it does not by itself cause an interrupt to be trapped but instead specifies an action when that event occurs.
The N option must be explicitly specified for all four subcommands (L S, T and C) when required.
It is not valid with the List subcommand.
The abbreviation * may be specified as an alternative to the following interrupts, in each of the refining categories:
Real-mode:
Vectors f and 10 are only allowed with OS/2 Warp SMP
Results & Notes:
Only the List subcommand gives immediate output, which is of the form in the following example:
---------------------------------------------------##VL R 0 1 2 3 4 5 6 V P d U e F e d ---------------------------------------------------
As can bee seen from this example each category is shown with its one-letter abbreviation followed by a list of interrupt vectors currently being intercepted by the Kernel Debugger
Notes:
The N option must be specified explicitly to be listed.
The U option is only from OS/2 Warp V3.0 fix pack 26 and OS/2 Warp V4.0 fix pack 1.
All other subcommands only cause output to appear when an interrupt is intercepted. When this happens the following events occur:
The following figure shows the format of the trap messages issued by the Kernel Debugger exception handlers:
Trap 0 - Divide Error Exception Trap 1 - Unexpected trace interrupt Trap 2 - NMI Interrupt Trap 4 - INTO Detected Overflow Exception Trap 5 - BOUND Range Exceeded Exception Trap 6 - Invalid Opcode Exception Trap 7 - Processor Extension Not Available Exception Trap 8 - Double Exception Detected nnnn Trap 9 - Processor Extension Segment Overrun Trap 10 (0AH) - Invalid TSS nnnn, mmmmmmmm Trap 11 (0BH) - Segment Not Present nnnn, mmmmmmmm Trap 12 (0CH) - Stack Segment Overrun or Not Present nnnn, mmmmmmmm Trap 13 (0DH) - General Protection Fault nnnn, mmmmmmmm Trap 14 (0EH) - Page Fault nnnn, mmmmmmm
In the messages above nnnn is substituted with the Intel exception code and mmmmmmmm is substituted with an interpretation of the Intel error code flags. For Trap 10, Trap 11, Trap 12 and Trap 13 the error code flags are interpreted as:
External
For Trap 14 the error code flags are interpreted as a combination of:
Not Present
If a trap occurs in the debugger component of the Kernel Debugger the trap message will be appended with:
- In Debugger
If this happens then the only hope of recovering the system is to set the registers, using the R command, to a known consistent set of values.
See the INTEL x86 Programmer's Reference or the INTEL Pentium User's Guide for further information on exceptions and error codes.
Notes
Trap 1 normally occurs as part of the operation of the Kernel Debugger. Only unexpected Trap 1 exception are therefore reported.
When a Trap 1 is generated through use of the Debug Registers then the Kernel Debugger signals this with the message Debug register hit.
Trap 3 occurs through use of the INT 3 instruction. This is used both by the Kernel Debugger and user programs in implementing break-points. User programs may use the INT 3 instruction as a program controlled technique for breaking into the debugger. In these cases a trap message is not displayed.